MPC8280 datasheet(1290/1386 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

39-6

Freescale Semiconductor

mode. Gaps should be inserted between multiple characters to keep from exceeding the maximum

sustained data rate.

39.4

Programming the SPI Registers

The following sections describe the registers used in configuring and operating the SPI.

39.4.1

SPI Mode Register (SPMODE)

The SPI mode register (SPMODE), shown in Figure 39-4, controls both the SPI operation mode and clock

source.

Table 39-1 describes the SPMODE fields.

1011

1213

1415

Field

—

LOOP

DIV16

REV

M/S

LEN

Reset

0000_00

—

0_0000_0000

R/W

Addr

0x11AA0

Figure 39-4. SPMODE—SPI Mode Register

Table 39-1. SPMODE Field Descriptions

Bits

Name

Description

—

Reserved, should be cleared.

LOOP Loop mode. Enables local loopback operation.

0 Normal operation.

1 Loopback mode. The transmitter output is internally connected to the receiver input. The receiver

and transmitter operate normally, except that received data is ignored.

Clock invert. Inverts SPI clock polarity. See Figure 39-5 and Figure 39-6.

0 The inactive state of SPICLK is low.

1 The inactive state of SPICLK is high.

Clock phase. Selects the transfer format. See Figure 39-5 and Figure 39-6.

0 SPICLK starts toggling at the middle of the data transfer.

1 SPICLK starts toggling at the beginning of the data transfer.

DIV16 Divide by 16. Selects the clock source for the SPI baud rate generator when configured as an SPI

master. In slave mode, SPICLK is the clock source.

0 BRGCLK is the input to the SPI BRG.

1 BRGCLK/16 is the input to the SPI BRG.

REV

Reverse data. Determines the receive and transmit character bit order.

0 Reverse data—lsb of the character sent and received first.

1 Normal operation—msb of the character sent and received first.

M/S

Master/slave. Selects master or slave mode.

0 The SPI is a slave.

1 The SPI is a master.

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