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MPC8280 데이터시트(PDF) 1304 Page - Freescale Semiconductor, Inc |
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MPC8280 데이터시트(HTML) 1304 Page - Freescale Semiconductor, Inc |
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1304 / 1386 page ![]() I 2C Controller MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 40-2 Freescale Semiconductor 40.1 Features The following is a list of the I2C controller’s main features: • Two-signal interface (SDA and SCL) • Support for master and slave I2C operation • Multiple-master environment support • Continuous transfer mode for automatic scanning of a peripheral • Supports a maximum clock rate of 2,080 KHz (with a CPM utilization of 25%), assuming a 100-MHz system clock. • Independent, programmable baud-rate generator • Supports 7-bit I2C addressing • Open-drain output signals allow multiple master configuration • Local loopback capability for testing 40.2 I2C Controller Clocking and Signal Functions The I2C controller can be configured as a master or slave for the serial channel. As a master, the controller’s BRG provides the transfer clock. The I2C BRG takes its input from the BRG clock (BRGCLK), which is generated from the CPM clock; see Section 10.4, “System Clock Control Register (SCCR).” SDA and SCL are bidirectional signals connected to a positive supply voltage through an external pull-up resistor. When the bus is free, both signals are pulled high. The general I2C master/slave configuration is shown in Figure 40-2. Figure 40-2. I2C Master/Slave General Configuration When the I2C controller is master, the SCL clock output, taken directly from the I2C BRG, shifts receive data in and transmit data out through SDA. The transmitter arbitrates for the bus during transmission and aborts if it loses arbitration. When the I2C controller is a slave, the SCL clock input shifts data in and out through SDA. The SCL frequency can range from DC to BRGCLK/48. 40.3 I2C Controller Transfers To initiate a transfer, the master I2C controller sends a message specifying a read or write request to an I2C slave. The first byte of the message consists of a 7-bit slave port address and a R/W request bit. Note that VDD VDD Master Slave (EEPROM, for example) SCL SCL SDA SDA |
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