MPC8280 datasheet(1305/1386 Pages) FREESCALE

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2C Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

40-3

because the R/W request follows the slave port address in the I2C bus specification, the R/W request bit

must be placed in the lsb (bit 7) unless operating in reverse data mode; see Section 40.4.1, “I2C Mode

To write to a slave, the master sends a write request (R/W = 0) along with either the target slave’s address

or a general call (broadcast) address of all zeros, followed by the data to be written. To read from a slave,

the master sends a read request (R/W = 1) and the target slave’s address. When the target slave

acknowledges the read request, the transfer direction is reversed, and the master receives the slave’s

transmit buffer(s). If the receiver (master or slave) does not acknowledge each byte transfer in the ninth

bit frame, the transmitter signals a transmission error event (I2ER[TXE]). An I2C transfer timing diagram

is shown in Figure 40-3.

Figure 40-3. I2C Transfer Timing

Select master or slave mode for the controller using the I2C command register (I2COM[M/S]). Set the

master’s start bit, I2COM[STR], to begin a transfer; setting a slave’s I2COM[STR] activates the slave to

wait for a transfer request from a master.

If a master or slave transmitter’s current TxBD[L] is set, transmission stops once the buffer is sent; that is,

I2COM[STR] must be set again to reactivate transfers. If TxBD[L] is zero, once the current buffer is sent,

the controller begins processing the next TxBD without waiting for I2COM[STR] to be set again.

The following sections further detail the transfer process.

40.3.1

I2C Master Write (Slave Read)

If the MPC8280 is the master, prepare the transmit buffers and BDs before initiating a write. Initialize the

first transmit data byte with the slave address and write request (R/W = 0).

If the MPC8280 is the slave target of the write, prepare receive buffers and BDs to await the master’s

request. Figure 40-4 shows the timing for a master write.

Figure 40-4. I2C Master Write Timing

SCL

SDA

Data Byte

Start Condition

Stop Condition

SDA

Device Address

Data Byte

Note: Data and ACK are repeated n times.

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