MPC8280 datasheet(1352/1386 Pages) FREESCALE

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MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Glossary-8

Freescale Semiconductor

Scalability. The capability of an architecture to generate implementations specific for a

wide range of purposes, and in particular implementations of significantly greater

performance or functionality than at present, while maintaining compatibility with

current implementations.

Scan chain. The peripheral buffers of a device, linked in JTAG test mode, which are

addressed in a shift-register fashion.

Set (v). To write a nonzero value to a bit or bit field; the opposite of clear. The term ‘set’

may also be used to describe updating of a bit or bit field.

Set (n). A subdivision of a cache. Cacheable data can be stored in a given location in any

one of the sets, typically corresponding to its lower-order address bits. Because

several memory locations can map to the same location, cached data is typically

placed in the set whose cache block corresponding to that address was used least

recently. See Set-associative.

Set-associative. Aspect of cache organization in which the cache space is divided into

sections, called sets. The cache controller associates a particular main memory

address with the contents of a particular set or region within the cache.

Significand. The component of a binary floating-point number that consists of an explicit

or implicit leading bit to the left of its implied binary point and a fraction field to

the right.

Slave. A device that responds to the master’s address. A slave receives data on a write cycle

and gives data to the master on a read cycle.

Static branch prediction. Mechanism by which software (for example, compilers) can

give a hint to the machine hardware about the direction a branch is likely to take.

Sticky bit. A bit that when set must be cleared explicitly.

Superscalar machine. A machine that can issue multiple instructions concurrently from a

conventional linear instruction stream.

Supervisor mode. The privileged operation state of a processor. In supervisor mode,

software, typically the operating system, can access all control registers and can

access the supervisor memory space, among other privileged operations.

Synchronization. A process to ensure that operations occur strictly in order. See Context

synchronization and Execution synchronization.

Synchronous exception. An exception that is generated by the execution of a particular

instruction or instruction sequence. The two types of synchronous exceptions are

precise and imprecise.

System memory. Physical memory available to a processor.

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