MPC8280 datasheet(1353/1386 Pages) FREESCALE

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MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Glossary-9

Time-division multiplex (TDM). A single serial channel used by several channels that

take turns.

TLB (translation lookaside buffer). A cache that holds recently used page table entries.

Throughput. The measure of the number of instructions that are processed per clock cycle.

UISA (user instruction set architecture). The level of the architecture to which user-level

software should conform. The UISA defines the base user-level instruction set,

user-level registers, data types, floating-point memory conventions and exception

models as seen by user programs, and the memory and programming models.

User mode. The unprivileged operating state of a processor used typically by application

software. In user mode, software can only access certain control registers and can

access only user memory space. No privileged operations can be performed. Also

referred to as 'problem state'

VEA (virtual environment architecture). The level of the architecture that describes the

memory model for an environment in which multiple devices can access memory,

defines aspects of the cache model, defines cache control instructions, and defines

the time-base facility from a user-level perspective. Implementations that conform

to the PowerPC VEA also adhere to the UISA, but may not necessarily adhere to

the OEA.

Virtual address. An intermediate address used in the translation of an effective address to

a physical address.

Virtual memory. The address space created using the memory management facilities of

the processor. Program access to virtual memory is possible only when it

coincides with physical memory.

Watchpoint. An event that is reported, but does not change the timing of the machine.

Word. A 32-bit data element. Note that on other processors a word may be a different size.

Write-back. A cache memory update policy in which processor write cycles are directly

written only to the cache. External memory is updated only indirectly, for

example, when a modified cache block is cast out to make room for newer data.

Write-through. A cache memory update policy in which all processor write cycles are

written to both the cache and memory.

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