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KING BILLION ELECTRONICS CO., LTD

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HE84G752B

HE80004 Series

January 21, 2005

V0.93

This specification is subject to change without notice. Please contact sales person for the latest version before use.

RATE

BAUD

FCK

DIVISOR

RATE

BAUD

, (FCK: fast clock of system)

The contents of BRH and BRL are calculated by the following two formulas:

BRL =

DIVISOR

RATE

BAUD

% 256

BRH = (

DIVISOR

RATE

BAUD

– BRL) / 256

The “%” symbol is the modulus operation (reminder of division). For example, if the FCK is 1.8432M Hz

and the desired baud rate is 2400 baud, then

2400

1843200

DIVISOR

RATE

BAUD

The BRL register shall be set to 0x30 and BRH set to 0x00. The setting of baud_rate_divisor is not

updated until the BRH register is written. Thus user is strongly recommended to write BRL first, then

BRH.

In order to obtain good communication quality, the same time base shall be used in the both sides of

transmitting and receiving. The following table shows the most common baud rate setting used in the PC

UART communication.

BRL and BRH: Baud Rate Control Registers

FCK(Hz)

Baud Rate (bps)

Divisor

BRL

BRH

1.8432M

2304

0x00

0x09

1.8432M

300

384

0x80

0x01

1.8432M

1200

0x60

0x00

1.8432M

2400

0x30

0x00

1.8432M

4800

0x18

0x00

1.8432M

9600

0x0C

0x00

1.8432M

19200

0x06

0x00

1.8432M

38400

0x03

0x00

1.8432M

57600

0x02

0x00

1.8432M

115200

0x01

0x00

19.3. Interrupt & Identification Register

This high nibble of IEIR register allows to enable/disable interrupt generation by the UART, the low

nibble ID[2..0] of IEIR register is used to identify the source of interrupts.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset Value

0x02h

IEIR

RLSI

THRI

RBRI

ID2

ID1

ID0

“0000_0000”

R/W

RBRI: Receiver Buffer Register Interrupt (1 = Enable, 0 = Disable), related to ID[1] bit.

THRI: Transmitter Hold Register Interrupt (1 = Enable, 0 = Disable), related to ID[0] bit.

RLSI: Receiver Line Status Interrupt (1 = Enable, 0 = Disable), related to ID[2] bit.

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