HE84G770B datasheet(5/61 Pages) KB

5 / 61 page

King Billion Electronics Co., Ltd

駿

億

電

子

股

份

有

限

公

司

HE84G770

HE80004H SERIES

October 31, 2003

Version:V1.1

This specification is subject to change without notice. Please contact sales person for the latest version before use.

Pin Name

I/O

Description

LCAP1A

O Charge Pump Capacitor Pin.

LVL5

P LCD Bias Voltage 5.

LVL4

P LCD Bias Voltage 4

LVL3

P LCD Bias Voltage 3

LVL2

P LCD Bias Voltage 2

LVL1

P LCD Bias Voltage 1.

LGS1

I Regulator Voltage Setting

LVREG

O Voltage Regulator Output. VDD is regulated to generate LVREG, which is in turns pumped

to LVL5. Adjust resistor between LGS1 and LVREG to set LVREG voltage.

VR12

I Charge Pump Input. The buffered output of the fine-adjusted VREG.

GND

P Power Ground Input.

O DAC Output.

DAO

O Alternate output of DAC.

OPIN

I Inverting input of OP Amp.

OPIP

I Non-inverting input of OP Amp.

OPO

O Output of OP Amp.

RSTP_N

I System Reset Input Pin. Level trigger, active low on this pin will put the chip in reset state.

FXO,

FXI

External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (‘0’ for RC

type and ‘1’ for crystal type). For RC type oscillator, one resistor needs to be connected

between FXI and GND. For crystal oscillator, one crystal needs to be placed between FXI

and FXO. Please refer to application for details.

TSTP_P

Test input pin. Please bond this pad and reserve a test point on PCB for debugging. But for

improving ESD, please connect this point with zero Ohm resistor to GND

SXO,

SXI

External slow clock pins. Slow clock is clock source for LCD display, TIMER1, Time-Base

and other internal blocks. Both crystal and RC oscillator are provided. The slow clock type

can be selected by mask option MO_SXTAL. Choose ‘0’ for RC type and ‘1’ for crystal

oscillator.

Input pin for x32 PLL circuit. Connect to external resistor and capacitors as shown in

application circuit.

OLFR

O LCD frame signal for interfacing with LCD segment extender KDGS80.

OCCK

O LCD data load pin for interfacing with LCD segment extender KDGS80.

VDD

Positive power Input. A 0.1 µF decoupling capacitors should be placed as close to IC VDD

and GND pads as possible for best decoupling effect.

PRTD[7..2]

PRTD[1]/SIN

PRTD[0]/SOUT

8-bit bi-directional I/O port D. The output type of I/O pad can also be selected by mask

option MO_DPP[7..0] (‘1’ for push-pull and ‘0’ for open-drain).

As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as

input, ‘1’ must be outputted before reading the pin.

PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be as external interrupt sources.

PRTD[1] shares pad with UART Receiver SIN pin.

PRTD[0] shares pad with UART transmitter SOUT pin.

GND_PWM

O Dedicated Ground for PWM output.

PWM

The PWM output can drive speaker or buzzer directly. Set the bit2 of VOC register as one to

turn on PWM. Using VDD & PWM to drive output device.

IRO

O The Infrared output.

PRTC[7..4]/

SCNI[3..0]

4-bit bi-directional I/O port C. The output type of I/O pad can also be selected by mask

option MO_CPP[7..4] (‘1’ for push-pull and ‘0’ for open-drain).

As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as

input, ‘1’ must be outputted before reading the pin.

PRTC[7..4] is shared with Key Scan Dedicated Input SCNI[3..0]. The Key Scan function

can be disabled by clearing MO_LCDKEY mask option to ‘0’.

VDD_RAM

P Dedicated power input for RAM

CMSG[32..79]

O COM[32..79] pads are shared with SEG[127..80] outputs. The functions of the pads to be

HE84G770B 데이터시트(PDF) 5 Page - King blillion Electronics Co.,Ltd.

HE84G770B 데이터시트(HTML) 5 Page - King blillion Electronics Co.,Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

데이터시트 다운로드

링크 URL