King Billion Electronics Co., Ltd

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HF88M02

January 16, 2004

Page 10 of 19

V1.11

This specification is subject to change without notice. Please contact sales person for the latest version before use.

6.6 Retrieving the Contents of Expansion I/O registers

The contents of all four registers can be read through data bus. The ability to access the contents of

registers avoids the necessity of using the RAM as mirror to keep the current status of latches in

applications. However, extra care should be taken when reading P0 and P1. To read the contents of P0

and P1, the DIR0 and DIR1 should be set to output mode. Otherwise, the pin status instead of P0 and P1

will be read. The same precaution should be applied in Read-Modify-Write sequence that read back the

contents of the output registers of output mode pins and input status of input mode pins.

7 Timing Diagrams

Symbol

Parameter

Min.

Typ.

Max.

Unit

Chip selected to active width

0

50

-

ns

WEn active low width

100

-

-

ns

WEn inactive low width

100

-

-

ns

Written data hold time

50

-

-

ns

Read-Write mode transient time

200

-

-

ns

ROM data file available time

50

-

-

ns

Output enable low duty for access ROM

250

-

-

ns

Output enable low duty for access ROM

150

-

-

ns

50

-

-

ns

Register data available time

30

-

-

ns

Output enable low duty for access register

100

-

-

ns

Output enable low duty for access register

100

-

-

ns

RS signal setup time

50

-

-

ns

RS signal hold time

50

-

-

ns