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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC912XDP512F0MPVR 데이터시트(PDF) 79 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 79 Page - Freescale Semiconductor, Inc |
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79 / 1350 page  MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 79 Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.1 Introduction This specification describes the function of the clocks and reset generator (CRG). 2.1.1 Features The main features of this block are: • Phase locked loop (PLL) frequency multiplier — Reference divider — Automatic bandwidth control mode for low-jitter operation — Automatic frequency lock detector — Interrupt request on entry or exit from locked condition — Self clock mode in absence of reference clock • System clock generator — Clock quality check — User selectable fast wake-up from Stop in self-clock mode for power saving and immediate program execution — Clock switch for either oscillator or PLL based system clocks • Computer operating properly (COP) watchdog timer with time-out clear window • System reset generation from the following possible sources: — Power on reset — Low voltage reset — Illegal address reset — COP reset — Loss of clock reset — External pin reset • Real-time interrupt (RTI) |
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