STW81101ATR datasheet(25/48 Pages) STMICROELECTRONICS

25 / 48 page

STW81101

I2C bus interface

25/48

Figure 21.

START and STOP conditions

6.1.3

Byte format and acknowledge

Every byte put on the SDA line must be 8 bits long, and be followed by an acknowledge bit

to indicate a successful data transfer. Data is transferred with the most significant bit (MSB)

first. The transmitter releases the SDA line after sending 8 bits of data. During the 9th clock

pulse, the receiver pulls the SDA line low to acknowledge the receipt of 8 bits of data.

Figure 22.

Byte format and acknowledge

6.1.4

Device addressing

The master must first initiate with a START condition to communicate with the STW81101,

and then send 8 bits (MSB first) on the SDA line which correspond to the device select

address and the read or write mode.

The first 7 MSBs are the device address identifier, which corresponds to the I2C bus

definition. For the STW81101, the address is set at “1100A2A1A0”, 3 bits programmable.

The 8th bit (LSB) is the read or write (RW) operation bit, which is set to 1 in read mode and

to 0 in write mode.

Following a START condition, the STW81103 identifies the device address on the bus and, if

matched, acknowledges the identification on the SDA bus during the 9th clock pulse.

SDA

SCL

START

STOP

SDA

SCL

START

Acknowledgement

from receiver

MSB

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