STW81101ATR datasheet(5/48 Pages) STMICROELECTRONICS

5 / 48 page

STW81101

List of figures

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List of figures

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2.

Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3.

VCO A (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 4.

VCO B (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5.

VCO A (direct output) closed loop phase noise at 3.6GHz

(FSTEP=200kHz; FPFD=200kHz; ICP=3.5mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6.

VCO B (direct output) closed loop phase noise at 4.0GHz

(FSTEP=200kHz; FPFD=200kHz; ICP=4mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7.

VCO A (div. by 2 output) closed loop phase noise at 1.8GHz

(FSTEP=200kHz; FPFD=400kHz; ICP=2mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8.

VCO B (div. by 2 output) closed loop phase noise at 2.0GHz

(FSTEP=200kHz; FPFD=400kHz; ICP=3mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9.

VCO A (div. by 4 output) closed loop phase noise at 900MHz

(FSTEP=200kHz; FPFD=800kHz; ICP=1.5mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10.

VCO B (div. by 4 output) closed loop phase noise at 1.0GHz

(FSTEP=200kHz; FPFD=800kHz; ICP=1.5mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11.

PFD frequency spurs (direct output; FPFD=200kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.

PFD frequency spurs (div. by 2 output; FPFD=400kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 13.

PFD frequency spurs (div. by 4 output; FPFD=800kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 14.

Settling time (final frequency=1.8 GHz; FPFD=400kHz; ICP=2mA . . . . . . . . . . . . . . . . . . . 16

Figure 15.

Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 16.

VCO divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 17.

PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 18.

Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 19.

VCO sub-bands frequency characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 20.

Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 21.

START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 22.

Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 23.

Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 24.

Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 25.

Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 26.

SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 27.

SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 28.

Differential/single-ended output network (MATCH_LC_LUMP_4G_DIFF.dsn) . . . . . . . . . 38

Figure 29.

LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) . . . . . . . . . . . . . . 39

Figure 30.

Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn) . . . . . . . . . . . . . . . . 40

Figure 31.

Differential/single-ended output network (MATCH_LC_LUMP_2G_DIFF.dsn) . . . . . . . . . 40

Figure 32.

LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) . . . . . . . . . . . . . . 41

Figure 33.

Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn) . . . . . . . . . . . . . . . . 41

Figure 34.

LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn) . . . . . . . . . . . . . . 42

Figure 35.

Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn) . . . . . . . . . . . . . . . . 43

Figure 36.

Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 37.

VFQFPN28 mechanical drawing (

Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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