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25PE20VP 데이터시트(PDF) 52 Page - STMicroelectronics

부품명 25PE20VP
상세설명  1 and 2 Mbit, low voltage, Page-Erasable Serial Flash memories with Byte-Alterability, 50 MHz SPI bus, standard pinout
PDF  60 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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25PE20VP 데이터시트(HTML) 52 Page - STMicroelectronics

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DC and AC parameters
M25PE20, M25PE10
52/60
Table 22.
AC characteristics (50 MHz operation, T9HX (0.11µm) process(1))(2) (3)
Test conditions specified in Table 16 and Table 17
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
fC
fC
Clock Frequency for the following instructions:
FAST_READ, RDLR, PW, PP, WRLR, PE, SE,
SSE, DP, RDP, WREN, WRDI, RDSR, WRSR
D.C.
50
MHz
fR
Clock Frequency for READ instructions
D.C.
33
MHz
tCH
(4)
tCLH Clock High Time
9
ns
tCL
(4)
tCLL
Clock Low Time
9
ns
Clock Slew Rate 2 (peak to peak)
0.1
V/ns
tSLCH
tCSS S Active Setup Time (relative to C)
5
ns
tCHSL
S Not Active Hold Time (relative to C)
5
ns
tDVCH
tDSU Data In Setup Time
2
ns
tCHDX
tDH
Data In Hold Time
5
ns
tCHSH
S Active Hold Time (relative to C)
5
ns
tSHCH
S Not Active Setup Time (relative to C)
5
ns
tSHSL
tCSH S Deselect Time
100
ns
tSHQZ
(5)
tDIS
Output Disable Time
8
ns
tCLQV
tV
Clock Low to Output Valid
8
ns
tCLQX
tHO
Output Hold Time
0
ns
tWHSL
(6)
Write Protect Setup Time
50
ns
tSHWL
(6)
Write Protect Hold Time
100
ns
tDP
(5)
S to Deep Power-down
3
µs
tRDP
(5)
S High to Standby Mode
30
µs
tW
Write Status Register Cycle Time
3
15
ms
tPW
(7)
Page Write Cycle Time (256 bytes)
11
23
ms
tPP
(7)
Page Program Cycle Time (256 bytes)
0.8
3ms
Page Program Cycle Time (n bytes)
int(n/8) × 0.025(8)
tPE
Page Erase Cycle Time
10
20
ms
tSE
Sector Erase Cycle Time
1
5
s
tSSE
SubSector Erase Cycle Time
40
150
ms
tBE
Bulk Erase Cycle Time
4.5
10
s
1.
See Important note on page 6.
2.
Preliminary data.
3.
Details of how to find the Technology Process in the marking are given in AN1995, see also Section 13: Part numbering.
4.
tCH + tCL must be greater than or equal to 1/ fC
5.
Value guaranteed by characterization, not 100% tested in production.
6.
Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
7.
When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence
including all the bytes versus several sequences of only a few bytes (1
≤n ≤256).
8.
int(A) corresponds to the upper integer part of A. E.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16.



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