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25PE20VP 데이터시트(PDF) 30 Page - STMicroelectronics

부품명 25PE20VP
상세설명  1 and 2 Mbit, low voltage, Page-Erasable Serial Flash memories with Byte-Alterability, 50 MHz SPI bus, standard pinout
PDF  60 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

25PE20VP 데이터시트(HTML) 30 Page - STMicroelectronics

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Instructions
M25PE20, M25PE10
30/60
6.6
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-Byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum
frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first Byte addressed can be at any location. The address is automatically incremented
to the next higher address after each Byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 13.
Read Data Bytes (READ) instruction sequence and data-out sequence
1.
Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the
M25PE10.
C
D
AI03748D
S
Q
23
2
1
3456789 10
28 29 30 31 32 33 34 35
22 21
3210
36 37 38
76543
1
7
0
High Impedance
Data Out 1
Instruction
24-Bit Address
0
MSB
MSB
2
39
Data Out 2



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