TMPR3916 datasheet(86/225 Pages) TOSHIBA

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Chapter 3 Graphics Display Controller (GDC)

Preliminary

3-7

Note that the use of external synchronization signals needs processing time. Therefore the input

signals HSYNC and VSYNC are delayed internally. To compensate this delay, set the horizontal

display-related registers -3, the vertical display-related registers need not be changed. For positive mode

set the horizontal display-related register –6 and the vertical display-related register -2.

When using external HSYNC and VSYNC signals, the horizontal synchronization pulse width

(HSWR), vertical synchronization pulse width (VSWR), horizontal cycle register (HCR) and vertical

cycle register (VCR) settings are invalid.

External composite synchronization signals cannot be processed by the TMPR3916.

Please note also that due to internal data structures HDS and HDE are automatically incremented by

8 so that the effective values are HDS+8 and HDE+8.

3.1.4

Dots and Pixels

The GDC is able to support both, dot and pixel on digital output. The 16-bit data for one dot is

divided into R (red), G (green), and B (blue). A pixel represents one of these colors in a 6-bit value. In

consequence one dot represents three pixels as shown in the following figure:

~10

0/1

R[5:0]

G[5:0]

B[5:0]

16-bit dot data

6-bit pixel data

0/1

Figure 3.1.9 Partitioning RGB Data into Dot and Pixel Data

Each six bits of RGB data are input to the 6-bit DAC (three channels) in the GDC. The LSB of R and

G transmitted to the DAC data are always fixed to zero.

In dot mode (DCR[3] = 0) the GDC supports dots on the digital RGB port (PIO[15:0]) and dot clock

on the DOTCLK port. In pixel mode (DCR[3] = 1) the GDC supports pixels on the lower 6 ports of the

digital RGB port (PIO[5:0]) and pixel clock on the DOTCLK port. Within the pixel mode the LSB of R

and G are equal to bit 4 of the DCR register (DCR[4]).

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