TMPR3916 datasheet(138/225 Pages) TOSHIBA

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Chapter 7 CAN Module (TXCAN)

Preliminary

7-17

The length of a bit is determined by the parameters TSEG1, TSEG2 and BRP. All controllers on the

CAN bus must have the same baud rate and bit length. At different clock frequencies of the individual

controllers, the baud rate has to be adjusted by the mentioned parameters. In the bit timing logic, the

conversion of the parameters to the required bit timing is realized. The configuration registers (BCR1,

BCR2) contain the data about the bit timing. Its definition corresponds to the CAN specification 2 (like

Intel 82527). The register content is zero after a reset.

Nominal Bit Time

SJW

TSEG2

TSEG1

SJW

SYNCSEG

Transmit Point

Sample Point

Figure 7.2.4 Required Timing Parameters for CAN Transmission

The length of TSCL (CAN Bus System Clock) is defined by:

OSC

SCL

BRP

SCL

∗

(TQ = time quantum)

fOSC is the TXCAN clock frequency (input clock of the TXCAN module). This clock is the output of

a prescaler with a divider ratio from 2 up to 8. This ratio can be set in the Chip Configuration Register

(CCR). The default setting is 3.

The synchronization segment SYNCSEG has always the length of one TSCL.

The baud rate is defined by:

SCL

)

TSEG

(

)

TSEG

((

∗

IPT (information processing time) is the time segment starting with the sample point reserved for

processing of the sampled bit level. The information processing time is equal to 3 TXCAN system clock

cycles.

The parameter SJW (2 bits) indicates, by how many units of TQ a bit is allowed to be lengthened or

shortened when re-synchronizing. Values between “1” (SJW = 00b) and “4” (SJW = 11b) are adjustable.

The bus line is sampled and a synchronization is performed at each falling edge of the bus signal within

a bit grid.

With the corresponding bit timing, it is possible to reach a multiple sampling of the bus line at the

sample point by setting SAM. The level determined by the CAN bus then corresponds to the result from

the majority decision of the last three values. The sample points are at the rising edges of the external

SamPoint signal and twice before with a distance of one TXCAN system clock cycle.

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