TMPR3916 datasheet(155/225 Pages) TOSHIBA

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Chapter 8 Parallel Interface (PORT)

Preliminary

8-2

Physical

Address (hex)

Function of One Bit

Reset

Value

PALMX

1C03 000C

Controls edge detection for interrupt generation

0 = Cause an interrupt on falling edge

1 = Cause an interrupt on rising edge

The contents of this register show no effect, if PAMSK is set to 0.

PAL

1C03 0008

Interrupt flag

0 = No interrupt has occurred on pin

1 = Interrupt has occurred on pin

Bits in this register are set, when a rising edge or a falling edge (depending

on PALMX setting) on the corresponding PIO pin is detected and the PIO

was enabled for interrupts (PAMSK). Flags are only set if the PIO is

configured to be an input (PACR) and is used by the PORT module

(PAMUX). Each flag can be reset to 0 by writing a 0 to it. Before you can

reset a PORT-interrupt in the interrupt controller, you must reset the interrupt

flag in PAL register.

Writing 1 to this register has no effect.

Pin Assignment

The PAMUX register in the PORT module and the SEIMUX bits in the Chip Configuration Register (CCR)

determine the use of the PIO pins. The following table shows the pin use and the corresponding bit settings:

PIO0 .. PIO15

PIO16 .. PIO29

PAMUX = 0

PORT

PAMUX = 1 and SEIMUX = 0

GDC

UART

PAMUX = 1 and SEIMUX = 1

GDC

TXSEI

Example for register configuration:

Task

Solution

pins 0 to 15 are used by GDC,

pins 16 to 29 are used by PORT

PAMUX = 0x0000FFFF

pins 16 to 20 are used as outputs,

pins 21 to 29 are used as inputs

PACR = 0x000F0000

following pins should cause an interrupt

- a signal change from low to high on pin 24

- a signal change from high to low on pin 25

PAMSK = 0x03000000

PALMX = 0x01000000

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