TMPR4937 datasheet(116/552 Pages) TOSHIBA

116 / 552 page

Chapter 7 External Bus Controller

7-16

7.3.7.4

ACK* Input Timing (External ACK Mode)

The ACK* signal becomes an input signal when in the external ACK mode.

During a Read cycle, data is latched two clock cycles after assertion of the ACK* signal is

acknowledged (Figure 7.3.9 ACK* Input Timing (Single Read Cycle)). During a Write cycle,

assertion of the ACK* signal is acknowledged, SWE*/BWE* is deasserted three clock cycles

later, then data is held for one clock cycle after that (Figure 7.3.10 ACK* Input Timing (Single

Write Cycle).

The ACK* input signal is internally synchronized. Due to internal State Machine restrictions,

ACK* cannot be acknowledged consecutively on consecutive clock cycles. External devices can

assert ACK* across multiple clock cycles under the following conditions.

•

During Single access, the ACK* signal can be asserted before the end of the cycle during

which CE* is dasserted.

•

During Burst access, it is possible to assert the ACK* signal for up to three clock cycles

during Reads and for up to five clock cycles during Writes. If the ACK* signal is asserted for

a period longer than this, it will be acknowledged as the next valid ACK* signal.

Figure 7.3.9 ACK* Input Timing (Single Read Cycle)

Figure 7.3.10 ACK* Input Timing (Single Write Cycle)

SYSCLK

CE*

ADDR [19:0]

OE*

DATA [31:0]

ACK*/READY (Input)

Latch Data

Acknowledge ACK*

2 clocks

EBCCRn.SHWT=0

SYSCLK

CE*

ADDR [19:0]

SWE*/BWE*

DATA [31:0]

ACK*/READY (Input)

3 clocks

4 clocks

Acknowledge ACK*

EBCCRn.SHWT=0

TMPR4937 데이터시트(PDF) 116 Page - Toshiba Semiconductor

TMPR4937 데이터시트(HTML) 116 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL