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TMPR4937 데이터시트(PDF) 112 Page - Toshiba Semiconductor

부품명 TMPR4937
상세설명  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4937 데이터시트(HTML) 112 Page - Toshiba Semiconductor

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Chapter 7 External Bus Controller
7-12
7.3.6.4
Page Mode
When in this mode, the ACK*/Ready pin becomes ACK* output when it is in the Dynamic
mode. When it is in the ACK*/Ready Static mode, the ACK*/Ready signal becomes HiZ.
Wait cycles are inserted into the access cycle according to the values of EBCCRn.PWT and
EBCCRn.WT. The Single access protocol in Page mode is identical to that of Normal mode,
except the number of wait cycles inserted. The Wait cycle count in the first access cycle of Single
access or Burst access is determined by the EBCCRn.WT value. The Wait cycle count can be set
from 0 to 15. The Wait cycle count of subsequent Burst cycles is determined by the
EBCCRn.PWT value. The Wait cycle count can be set from 0 to 3.
Figure 7.3.4 Page Mode (Burst Access)
SYSCLK
CE*
ADDR [19:0]
OE*
DATA [31:0]
ACK*/READY (Output)
EBCCRn.WT=2
EBCCRn.PWT=1
EBCCRn.PWT=1
EBCCRn.PWT=1



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