TMPR4937 datasheet(238/552 Pages) TOSHIBA

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Chapter 9 SDRAM Controller

9-22

9.4.3

SDRAM Command Register (SDCCMD)

0x8058

Reserved

:Type

:Initial value

Reserved

:Type

:Initial value

MDLNO

VERNO

:Type

0x30

0x10

:Initial value

Reserved

CCE

CMD

R/W

:Type

0x0

:Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

63:32

—

Reserved

⎯

31:24

MDLNO

Model Number

Model Number (Default: 0x30)

Indicates the model number. The default value is 0x30 for the TX4937.

This field is Read Only.

23:16

VERNO

Version Number

Version Number (Default: 0x10)

Indicates the version number. The default value is 0x10 for the TX4937.

This field is Read Only.

15:8

—

Reserved

⎯

7:4

CCE

Command

Channel Enable

Command Channel Enable

Setting one of these bits to “1” enables the command of the corresponding

channel. This command is simultaneously executed on all channels that

are enabled.

bit 7: Channel 3

bit 6: Channel 2

bit 5: Channel 1

bit 4: Channel 0

R/W

3:0

CMD

Command

Specifies a command that is performed on memory.

0x0: NOP command

0x1: Set Mode Register command

Set SDRAM Mode Register from SDCTR value

0x2: Reserved

0x3: Precharge All command

Precharge All SDRAM Banks

0x4: Self-Refresh Mode command

Sets SDRAM to the Self-Refresh Mode

0x5: Power Down Mode Command

Set SDRAM to the Power Down Mode

0x6: Normal Mode Command

Cancel Self-Refresh/Power Down Mode

0x7-0xf: Reserved

R/W

Figure 9.4.3 SDRAM Command Register

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