TMPR4956C datasheet(85/286 Pages) TOSHIBA

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Chapter 3 TX49/H4 Core’s Registers

3-25

3.2.19

DEPC Register (Reg

#24)

The DEPC register holds the address where processing resumes after the debug exception routine has

finished. The address that has been loaded in the DEPC register is the virtual address of the instruction

that caused the debug exception. If the instruction is in the branch delay slot, the virtual address of the

immediately preceding branch or jump instruction is placed in this register. Execution of the DERET

instruction causes a jump to the address in the DEPC. If the DEPC is both written from software (by

MTC0) and by hardware (debug exception) then the DEPC is loaded by the value generated by the

hardware.

Figure 3.2.19 shows the formats of the DEPC register and Table 3.2.20 describes the DEPC register

field.

DEPC

(32-bit mode)

DEPC

(64-bit mode)

Figure 3.2.19 DEPC Register Formats

Table 3.2.20 DEPC Register Field Description

32-bit mode

Bit(s)

Field Name

Description

Cold Reset

Read/Write

31:0

DEPC

Debug exception program counter.

Undefined

Read/Write

64-bit mode

Bit(s)

Field Name

Description

Cold Reset

Read/Write

63:0

DEPC

Debug exception program counter.

Undefined

Read/Write

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