TMPR4956C datasheet(93/286 Pages) TOSHIBA

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Chapter 3 TX49/H4 Core’s Registers

3-33

Before returning from a floating-point exception, software must first clear the enabled Cause bits

with a CTC1 instruction to prevent a repeat of the interrupt. Thus, User mode programs can never

observe enabled Cause bits set; if this information is required in a User mode handler, it must be

passed somewhere other than the Status register.

For a floating-point operation that sets only unenabled Cause bits, no floating-point exception

occurs and the default result defined by IEEE 754 is stored. In this case, the exceptions that were

caused by the immediately previous floating-point operation can be determined by reading the

Cause field.

Flag Bits

The Flag bits are cumulative and indicate the exceptions that were raised by the operations that

were executed since the bits were explicitly reset. Flag bits are set to 1 if an IEEE 754 exception is

raised, otherwise they remain unchanged. The Flag bits are never cleared as a side effect of

floating-point operations; however, they can be set or cleared by writing a new value into the Status

Control/Status Register Rounding Mode Control Bits

Bits 1 and 0 in the Control/Status register constitute the Rounding Mode (RM) field.

As shown in Table 3.3.5, these bits specify the rounding mode that CP1 uses for all floating-point

operations.

Table 3.3.5 Rounding Mode Bit Decoding

Rounding

ModeRM

[1:0]

Mnemonic

Description

Round result to nearest representable value; round to value with least-significant bit

0 when the two nearest representable values are equally near.

Round toward 0: round to value closest to and not greater in magnitude than the

infinitely precise result.

Round toward +

∞: round to value closest to and not less than the infinitely precise

result.

Round toward

−∞: round to value closest to and not greater than the infinitely precise

result.

3.3.3

Accessing the FP Control and Implementation/Revision Registers

The Control/Status and the Implementation/Revision registers are read by a Move Control From

Coprocessor 1 (CFC1) instruction.

The bits in the Control/Status register can be set or cleared by writing to the register using a Move

Control To Coprocessor 1 (CTC1) instruction. The Implementation/Revision register is a read-only

registers.

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