TMP88CS77F datasheet(62/140 Pages) TOSHIBA

62 / 140 page

3-77-62

TMP88CP77/S77/U77

2007-10-23

2.6.2

Control

The timer / counter 1 is controlled by a timer / counter 1 control register (TC1CR) and two 16-bit timer

registers (TREG1A and TREG1B). Reset does not affect TREG1A and TREG1B.

Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz]

Note 2: Writing to the lower byte of the timer registers (TREG1AL, TREG1BL), the comparison is inhibited until the

upper byte(TREG1AH, TREG1BH) is written. Only the lower byte of the timer registers can not be changed.

After writing to the upper byte, any match during 1 machine cycle (instruction execution cycle) is ignored.

Note 3: Set the mode, source clock, edge (including INT2ES) when TC1 stops (TC1S=00).

Note 4: Software capture can be used in only timer and event counter modes. SCAP1 is automatically cleared to

“0” after capturing.

Note 5: Values to be loaded to timer registers must satisfy the following condition.

TREG1A>0

Note 6: TC1CR and TREG1A are write-only registers and must not be used with any of the read-modify-write

instructions such as SET, CLR, etc.

Note 7: Please use the auto-capture function in the operative condition of TC1.

A captured value may not be fixed if it's read after the execution of the timer stop or auto-capture

disable. Please read the capture value in a capture enabled condition.

Note 8: Since the up-counter value is captured into TC1DRB by the source clock of up-counter after

setting TC1CR<ACAP1> to “1”. Therefore, wait at least one cycle of the internal source clock

before reading TC1DRB for the first time.

Figure 2-19. Timer Registers and TC1 Control Register

Timer Register 1

TREG1A

(00016, 00017H)

TREG1AH (00017H)

TREG1AL (00016H)

Write only

TREG1B

(00012, 00013H)

TREG1BH (00013H)

TREG1BL (00012H)

Read only

Timer Counter 1 Control Register

7654

3210

TC1CR

(00014H)

“1”

SCAP1

MCAP1

METT1

TC1S

TC1CK

TC1M

(Initial value: *000 0000 )

TC1M

TC1 operating mode select

00: Timer / external trigger timer / event counter mode

01: Window mode

10: Pulse width measurement mode

11: reserved

TC1CK

TC1 source clock select [Hz]

NORMAL1/2, IDLE1/2 mode

SLOW,

SLEEP

mode

DV7CK = 0

DV7CK = 1

DV1CK = 0

DV1CK = 1

DV1CK = 0

DV1CK = 1

fc/211

fc/212

fs/23

fc/27

fc/28

fc/27

fc/28

fc/23

fc/24

fc/23

fc/24

External clock (TC1 pin input)

Write

only

TC1S

TC1 start control

00: Stop & counter clear

01: Command start

10: Reserved

11: External trigger start

SCAP1

Software capture control

1: Software capture trigger

MCAP1

Pulse width measurement

mode control

0: Double edge capture

1: Single edge capture

METT1

External trigger timer mode

control

0: Trigger start

1: Trigger start & stop

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