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TMP88CS77F 데이터시트(PDF) 66 Page - Toshiba Semiconductor

부품명 TMP88CS77F
상세설명  CMOS 8-BIT MICROCONTROLLER
PDF  140 Pages
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP88CS77F 데이터시트(HTML) 66 Page - Toshiba Semiconductor

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3-77-66
TMP88CP77/S77/U77
2007-10-23
(4) Window mode
Counting up is performed on the rising edge of the pulse that is the logical AND-ed product of the TC1
pin input (window pulse) and an internal clock. The contents of TREG1A are compared with the
contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is
cleared. Positive or negative logic for the TC1 pin input can be selected. Edge selection is the same as
for INT2 pin. Setting SCAP1 to “1” transfers the current contents of up-counter to TREG1B.
It is necessary that the maximum applied frequency be such that the counter value can be analyzed by
the program. That is; the frequency must be considerably slower than the selected internal clock.
Figure 2-23. Window Mode Timing Chart
(5) Pulse width measurement mode
Counting is started by the external trigger (set to external trigger start by TC1S). The trigger can be
selected either the rising or falling edge of the TC1 pin input. The source clock is used an internal clock.
On the next falling (rising) edge, the counter contents are transferred to TREG1B and an INTTC1
interrupt is generated. The counter is cleared when the single edge capture mode is set. When double
edge capture is set, the counter continues and, at the next rising (falling) edge, the counter contents
are again transferred to TREG1B. If a falling (rising) edge capture value is required, it is necessary to
read out TREG1B contents until a rising (falling) edge is detected. Falling or rising edge is selected with
INT2ES, and single edge or double edge is selected with MCAP1 (bit 6 in TC1CR).
Note:
The first captured value after the timer starts may be read incorrectively, therefore, ignore the
first captured value.
Match detect
TREG1A
INTTC1 interrupt
Internal clock
Up-counter
TREG1A
TC1 pin input
Internal clock
Up-counter
TC1 pin input
INTTC1 interrupt
(a) Positive logic (at INT2ES=0)
(b) Negative logic (at INT2ES=1)
?
?
Match detect
1
0
7
47
5
46
31
2
1
0
7
5
3
6
2
0
2
3
Counter clear
Command start
89
0
1
9
Command start
Counter clear



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