TMP88CS43FG datasheet(97/218 Pages) TOSHIBA

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Page 87

TMP88CS43FG

9.3 Function

Compare timer/counter 1 has three modes: timer, event counter, and programmable pulse generator output modes.

9.3.1 Timer mode with software start

In this mode, the timer/counter (16-bit counter) counts up synchronously with the internal clock. When the

counter value and the set value of Compare Timer Register 1 (CTC1DRA) match, an INTCTC1 interrupt is

generated and the counter is cleared. After the counter is cleared, it restarts and continues counting up.

Figure 9-2 Timer Mode Timing Chart

Note:If the CTC input port (P47) is set for input mode, the timer/counter is reset by an input edge on port. When

using the timer/counter as an ordinary timer, set CTC1CR2<EXTRGDIS> to 1 or set P47 for output mode.

Table 9-1 Internal Clock Source for Compare Timer/Counter 1 (Example: fc = 20 MHz)

CTC1CK

NORMAL and IDLE Modes

DV1CK = 0

DV1CK = 1

Resolution [

µs]

Maximum Setting Time [s]

Resolution [

µs]

Maximum Setting Time [s]

000

102.4

6.71

204.8

13.42

001

6.4

0.419

12.8

0.839

010

1.6

0.105

3.2

0.210

011

0.4

26.21 m

0.8

52.43 m

100

0.2

13.11 m

0.4

26.21 m

101

0.1

6.55 m

0.2

13.11 m

110

n - 1

Timer Register A

Internal clock

Counter

INTCTC1 interrupt

Successive

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