TMP86CS44UG datasheet(48/172 Pages) TOSHIBA

48 / 172 page

Page 38

3. Interrupt Control Circuit

3.4 Interrupt Sequence

TMP86CS44UG

Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored

Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first

machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set.

Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction

Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt

service program

Figure 3-2 Vector table address,Entry address

A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than the

level of current servicing interrupt is requested.

In order to utilize nested interrupt service, the IMF is set to “1” in the interrupt service program. In this case,

acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.

To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced,

before setting IMF to “1”. As for non-maskable interrupt, keep interrupt service shorten compared with length

between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply

nested.

3.4.2 Saving/restoring general-purpose registers

During interrupt acceptance processing, the program counter (PC) and the program status word (PSW,

includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are

saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using

the same data memory area for saving registers. The following methods are used to save/restore the general-

purpose registers.

c + 1

Execute

instruction

Execute

instruction

− 2

n - 3

− 2n − 1

− 1

a + 2

a + 1

c + 2

b + 3

b + 2

b + 1

a + 1

− 1

Execute RETI instruction

Interrupt acceptance

Execute

instruction

Interrupt service task

1-machine cycle

Interrupt

request

Interrupt

latch (IL)

IMF

D2H

03H

D203H

D204H

06H

Vector table address

Entry address

0FH

Vector

Interrupt

service

program

FFF2H

FFF3H

TMP86CS44UG 데이터시트(PDF) 48 Page - Toshiba Semiconductor

TMP86CS44UG 데이터시트(HTML) 48 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL