STR750FV1H6 datasheet(5/84 Pages) STMICROELECTRONICS

5 / 84 page

STR750Fxx STR751Fxx STR752Fxx STR755Fxx

Introduction

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Introduction

This Datasheet contains the description of the STR750F family features, pinout, Electrical

Characteristics, Mechanical Data and Ordering information.

For complete information on the Microcontroller memory, registers and peripherals. Please

refer to the STR750F Reference Manual.

For information on the ARM7TDMI-S core please refer to the ARM7TDMI-S Technical

Reference Manual available from Arm Ltd.

For information on programming, erasing and protection of the internal Flash memory

please refer to the STR7 Flash Programming Reference Manual

For information on third-party development tools, please refer to the http://www.st.com/mcu

website.

3.1

Functional description

The STR750F family includes devices in 2 package sizes: 64-pin and 100-pin. Both types

have the following common features:

ARM7TDMI-STM core with embedded Flash & RAM

STR750F family has an embedded ARM core and is therefore compatible with all ARM tools

and software. It combines the high performance ARM7TDMI-STM CPU with an extensive

range of peripheral functions and enhanced I/O capabilities. All devices have on-chip high-

speed single voltage FLASH memory and high-speed RAM.

Figure 1 shows the general block diagram of the device family.

Embedded Flash memory

Up to 256 KBytes of embedded Flash is available in Bank 0 for storing programs and data.

An additional Bank 1 provides 16 Kbytes of RWW (Read While Write) memory allowing it to

be erased/programmed on-the-fly. This partitioning feature is ideal for storing application

parameters.

●

When configured in burst mode, access to Flash memory is performed at CPU clock

speed with 0 wait states for sequential accesses and 1 wait state for random access

(maximum 60 MHz).

●

When not configured in burst mode, access to Flash memory is performed at CPU

clock speed with 0 wait states (maximum 32 MHz)

Embedded SRAM

16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

Enhanced interrupt controller (EIC)

In addition to the standard ARM interrupt controller, the STR750F embeds a nested interrupt

controller able to handle up to 32 vectors and 16 priority levels. This additional hardware

block provides flexible interrupt management features with minimal interrupt latency.

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