Circuit description

STV7622

12/32

5.6

Power output block and EMI control

The high-voltage output stage has a totem pole structure (see Figure 3). The capacitive load

is charged to Vpp by the high-side N-channel transistor, T1, and discharged to ground by

the low-side N-channel transistor, T2. The status of the power outputs can also be controlled

by the configuration pins, POC and /BLK, which can set the power outputs either all High or

all Low.

Several functions, patented by STMicroelectronics, are implemented in the STV7622 to

reduce EMI:

SmartSlope: The falling edge of the output pulse consist of 2 slopes (Figure 6 below): a

smooth slope followed by a steeper one (typically 4 times faster) The duration of the first

slope is set by two logic inputs, FS1 and FS2, according to the table in Figure 6.

Figure 6.

Output falling edge

ConstantSlope: The duration of the output rising edge (Figure 7) is kept constant

independent of the value of the capacitive load connected to the output. This solution

minimizes the peak current in the power outputs as well as any oscillation phenomenon in

the power supplies. In addition, it reduces high-frequency components of the EMI spectrum

by suppressing very rapid rising edge transitions on the power outputs. The total duration of

table in Figure 7 below.

Figure 7.

Output rising edge

90%

10%

t

F-SLOW

t

F-OUT

100ns

0

1

200ns

1

1

50ns

1

0

10ns

0

0

t

F-SLOW

FS1

FS2

90%

10%

t

R-OUT

R

S1

=1

RS

2=

1

400ns

0

1

560ns

1

1

230ns

1

0

120ns

0

0

t

R-OUT

RS1

RS2