| 전자부품 데이터시트 검색엔진 |
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MAS9090BS 데이터시트(PDF) 7 Page - Micronas |
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MAS9090BS 데이터시트(HTML) 7 Page - Micronas |
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7 / 30 page ![]() DA9090B.001 January 14, 1998 7 TIMING SPECIFICATIONS x Serial Control Port Timing Parameter Symbol Conditions Min Typ Max Unit Frequency of CCLK fCCLK 2.048 MHz Period of CCLK high tWHC Measured from VIH to VIH 160 ns Period of CCLK low tWLC Measured from VIL to VIL 160 ns Rise time of CCLK tRC Measured from VIL to VIH 50 ns Fall time of CCLK tFC Measured from VIH to VIL 50 ns Hold time, CCLK high to CS low tHCHS 10 ns Setup time, CS low to CCLK high tSSLCH 50 ns Setup time, valid CI data to CCLK high tSDCH 50 ns Hold time, CCLK high to invalid CI data tHCHD 50 ns Delay time, CCLK low to valid CO data tDCLD Load = 100 pF 80 ns Delay time, CS low to valid CO data tDSD 50 ns Delay time, CS high or 8 th CCLK low to CO high impedance tDSZ 10 80 ns Hold time, 8 th CCLK high to CS high tH8CHS 100 ns Setup time, CS high to CCLK high tSSHCH 100 ns x Serial Control Port Timing Diagram (MICROWIRE mode) CCLK CS CI CO 1 2 3 4 5 67 8 1 2 3 4 5 67 8 76 5 4 3 2 1 0 76 5 4 3 2 1 0 76 5 4 3 2 1 0 t WHC t WLC t RC t FC t SSLCH t HCHS t SDCH t HCHD t HCHSH tSSLCH t SSHCH t HCHS t DSD t DCLD t DSZ t HCHSH BYTE 2 BYTE 1 |
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