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MAS9090BS 데이터시트(PDF) 2 Page - Micronas

부품명 MAS9090BS
상세설명  LOW VOLTAGE 14-BIT LINEAR CODEC
PDF  30 Pages
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제조업체  MICRONAS [Micronas]
홈페이지  http://www.micronas.com
Logo MICRONAS - Micronas

MAS9090BS 데이터시트(HTML) 2 Page - Micronas

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DA9090B.001
January 14, 1998
2
PIN CONFIGURATION
VCCA
VCCP
NC
NC
SP1-
SP1+
SP2-
SP2+
GNDP
RX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CCLK
CS
CI
BZ
VCC
CO
TX
GND
FS
MCLK
LO
MIC2-
MIC2+
MIC1-
MIC1+
GNDA
MIC3-
MIC3+
SO28
N
C
N
C
N
C
NC
NC
N
C
N
C
N
C
NC
NC
NC
NC
NC
N
C
N
C
SP1-
SP1
SP2-
SP2
GNDP
RX
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
C
C
L
K
C
S
C
I
B
Z
V
C
C
C
O
T
X
G
N
D
FS
MCLK
LO
MIC2-
MIC2+
MIC1-
M
I
C
1
+
G
N
D
A
M
I
C
3
-
M
I
C
3
+
NC
NC
NC
V
C
C
A
V
C
C
P
TQFP44
PIN DESCRIPTION
Pin Name
Pin Number
Type
Function
SO28
TQFP44
1,4
1,4,7,9
11,12,13
22,23,27
28,29,32
35,39,40,
43,44
No connection.
VCCA
2
41
P
Positive power supply input for analog section.
VCCP
3
42
P
Positive power supply input for speaker amplifiers.
SP1-
5
2
AO
Speaker 1 amplifier negative output.
SP1+
6
3
AO
Speaker 1 amplifier positive output.
SP2-
7
5
AO
Speaker 2 amplifier negative output.
SP2+
8
6
AO
Speaker 2 amplifier positive output.
GNDP
9
8
G
Speaker amplifier.
RX
10
10
DI
Receive data input.
CCLK
11
14
DI
Control clock input. Shifts serially into CI and CO when CS is
low. CCLK is asynchronous with other system clocks.
CS
12
15
DI
Chip select input.
CI
13
16
DI
Control data input.
BZ
14
17
AO
Buzzer driver output.
VCC
15
18
P
Positive power supply input for the digital section. VCCA,
VCCP AND VCC must be connected together.
CO
16
19
DO
Control data output.
TX
17
20
DO
Transmit data output. Data is shifted out on this during the
assigned transmit slots. Otherwise, TX is on high impedance
state.
GND
18
21
G
Ground for the digital section.
FS
19
24
DI
Frame sync input. This 8kHz signal defines the start of the TX
and RX frames.



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