10

Debug ROM Table

The Debug ROM table contains a list of components in the system. Debuggers can use

the Debug ROM table to determine which CoreSight components are implemented.

Power management and clock gating

The DebugBlock implements two Q-Channel interfaces, one for requests to gate the PCLK

clock and a second for requests to control the debug power domain.

Processor Interfaces

Name

Protocol

Width

Details

Low-latency

Peripheral Port

(LLPP)

AMBA 5 AXI

32-bit

Optional private LLPP per

core for minimum latency

access to memory and

devices outside the cluster.

Generic Interrupt

Controller (GIC)

Stream interface

AMBA 4 AXI4-Stream

32-bit

AXI-4 Stream interface for

interrupts between the

Cortex-R82 processor and

the system components.

DebugBlock

AMBA 4 APB

32-bit

APB interface between the

Cortex-R82 processor and

the DebugBlock.

Low-latency RAM

(LLRAM)

AMBA 5 AXI

256-bit

Optional LLRAM for low

latency access to memory

shared between cores within

the cluster.

Trace

AMBA 4 ATB

32-bit

instruction

ATB trace

128-bit data

ATB trace

Two master ATB interfaces

for instructions and data.

An instruction trace funnel

funnels all the processor ETM

instruction trace streams into

a single ATB trace bus. A data

trace funnel funnels all the

processor ETM data trace

streams and all the ELA trace

streams into a single ATB

trace bus.

Utility bus

AMBA 5 AXI

64-bit

Manages power states and

provides access to Power

Policy Units (PPUs)

registers and Reliability,

Availability, and Serviceability

(RAS) registers in each core

and the cluster.