ST10F272M datasheet(163/175 Pages) STMICROELECTRONICS

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ST10F272M

Electrical characteristics

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24.8.18

CLKOUT and READY

VDD = 5V ± 10%, VSS = 0V, TA = -40 to + 125°C, CL = 50pF

Table 72.

CLKOUT and READY timings

Symbol

Parameter

fCPU = 40 MHz

TCL = 12.5ns

Variable CPU clock

1/2 TCL = 1 to 40 MHz

Unit

MinMax

t29 CC CLKOUT cycle time

2TCL

t30 CC CLKOUT high time

–

TCL - 3.5

–

t31 CC CLKOUT low time

–

TCL - 2.5

–

t32 CC CLKOUT rise time

–4–4

t33 CC CLKOUT fall time

–4–4

t34 CC CLKOUT rising edge to ALE falling edge

-2 + tA

8 + tA

-2 + tA

8 + tA

t35 SR

Synchronous READY setup time to

CLKOUT

–17–

t36 SR

Synchronous READY hold time after

CLKOUT

2–2–

t37 SR Asynchronous READY low time

–

2TCL + 10

–

t58 SR Asynchronous READY setup time

(1)

–17–

t59 SR Asynchronous READY hold time

(1)

2–2–

t60 SR

Asynchronous READY hold time after RD,

WR high (Demultiplexed Bus)(2)

02tA + tC + tF

These timings are given for characterization purposes only, in order to assure recognition at a specific clock edge.

Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even

more time for deactivating READY. 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.

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