ST10F272M datasheet(36/175 Pages) STMICROELECTRONICS

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Internal Flash memory

ST10F272M

36/176

5.5.3

Flash non-volatile access protection register 0 (FNVAPR0)

5.5.4

Flash non-volatile access protection register 1 low (FNVAPR1L)

Table 19.

Flash non-volatile write protection I register

Bit

Name

Function

7:0

W0P[7:0]

Write Protection Bank 0 / Sectors 7-0 (IFlash)

These bits, if programmed at 0, disable any write access to the sectors of Bank 0

(IFlash)

FNVAPR0 (0x08 DFB8)

NVR

Delivery value: ACFFh

987

65432

Reserved

DBGP ACCP

-RW

Table 20.

Flash non-volatile access protection register 0

Bit

Name

Function

0ACCP

Access Protection

This bit, if programmed at 0, disables any access (read/write) to data mapped

inside IFlash Module address space, unless the current instruction is fetched from

IFlash.

1DBGP

Debug Protection

This bit, if erased at 1, can be used to by-pass all the protections using the Debug

features through the Test Interface. If programmed at 0, on the contrary, all the

debug features, the Test Interface and all the Flash Test modes are disabled. Even

STMicroelectronics will not be able to access the device to run any eventual failure

analysis.

FNVAPR1L (0x08 DFBC)

NVR

Delivery value: FFFFh

987

65432

PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDS0

Table 21.

Flash non-volatile access protection register 1 low

Bit

Name

Function

15:0 PDS[15:0]

Protections Disable 15-0

If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit ACCP

is disabled. Bit PDS0 can be programmed at 0 only if both bits DBGP and ACCP

have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit

PENx-1 has already been programmed at 0.

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