ST10F271B datasheet(133/180 Pages) STMICROELECTRONICS

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ST10F271B/ST10F271E

Electrical characteristics

133/180

Figure 37.

Port2 test mode structure

10. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is

illustrated in the

Figure 38 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs

disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: this implies I/O current is not considered. The device is

doing the following:

- Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM

- Watchdog Timer is enabled and regularly serviced

- RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles

- Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling

- Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)

- ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5

- All interrupts generated by XPWM, RTC, Timers and ADC are not serviced

11. The Idle mode supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is

illustrated in the

Figure 37 below. These parameters are tested and at maximum CPU clock with all outputs disconnected

and all inputs at VIL or VIH, RSTIN pin at VIH1min.

12. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD

– 0.1 V to VDD, VAREF = 0 V, all outputs (including pins configured as outputs) disconnected. Besides, the Main Voltage

Regulator is assumed off: in case it is not, additional 1mA shall be assumed.

Input

latch

Clock

P2.0

CC0IO

Output

buffer

Test mode

Alternate data input

Fast external interrupt input

Flash sense amplifier

and column decoder

ST10F271B 데이터시트(PDF) 133 Page - STMicroelectronics