| 전자부품 데이터시트 검색엔진 |
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IRGPC50FD2 데이터시트(PDF) 27 Page - International Rectifier |
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IRGPC50FD2 데이터시트(HTML) 27 Page - International Rectifier |
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27 / 35 page ![]() TEMPERATURE CYCLING (T/C) Unbiased Conditions Temperature: Tmin = - 55°C Tmax = + 150°C Bias: Unbiased Duration: 2000 Cycles Test points: 250,500,1000,1500,2000 Nominal Purpose Failure Modes Sensitive Parameters ICES,V(BR)CES, RθJC,VCE(on) Temperature Cycling simulates the extremes of thermal stresses which devices will encounter in the actual circuit applications in combination with potentially extreme operating ambient temperatures. Some equipment is destined to be used in extreme environments, and subject to daily temperature cycles. The primary failure mode for temperature cycling is a thermal fatigue of the silicon / metal interfaces and metal / metal interfaces. The fatigue results from thermomechanical stresses due to heating and cooling and will cause electrical or thermal performance to degrade. If the degradation occurs at the header / die interface, then the thermal impedance, RθJC will begin to increase well before any electrical effect is seen. If the degradation occurs at the wire bond / die interface or the wire bond / bond post interface, then on resistance, VCE(on), will slowly increase or become unstable with time. The thermal impedance, when measured during this time, may appear to decrease or change erratically. The mechanical stresses from the temperature can also propagate fractures in the silicon when the die is thermally mismatched to the solder / heat sink system. These fractures will manifest themselves in the form of shorted gates or degraded breakdown characteristics (V(BR)CES) IGBT / CoPack Quarterly Reliability Report Page 27 of 35 |
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