AS3953B datasheet(29/65 Pages) AMSOSRAM

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[v1-04] 2016-Jan-07

AS3953B − Detailed Description

Figure 36:

Configuration Word (Bits 14 to 0)

Note(s):

1. Configuration bits b31 to b15 define AS3953B response to SAK and ATS command in ISO 14443A Protocol mode, while bits b14 to

b0 actually change performance.

2. Applicable in ISO 14443A Level-3 and Level-4 Protocol modes.

3. Applicable in ISO 14443A Level-3 Protocol mode and Framing mode, in Protocol mode applicable for frames which are put in FIFO.

4. Configuration bits fdel<1:0> are used to adjust frame delay time PCD-to-PICC. Delays caused by reader and tag resonant tanks and

AFE processing are compensated by PICC logic.Figure below defines PCD-to-PICC frame delay compensation using fdel bits.

Configuration Bit

Name

Default

Function

b14

irq_pu

1: Send a power-up IRQ (after power-up

initialization is finished)

b13

irq_l4

1: Send an IRQ at entry in ACTIVE(*) state (after

sending SAK on Cascade Level 2) (2)

b12

mod_1

00: ISO 14443A Level-4 Protocol mode

01: ISO 14443A Level-3 Protocol mode

10: Framing mode

11: Transparent mode

b11

mod_0

b10

rxncrc

1: Rx – CRC is not checked, CRC part of message is

also put in FIFO (3)

rxbs

1: Rx – Bit stream mode, received bits are put in

FIFO (no parity and CRC check) (3)

txncrc

1: Tx – Do not generate CRC (3)

txbs

1: Tx – Bit stream mode, bits put in FIFO are sent

without parity and CRC generation (3)

fdel<1>

PCD-to-PICC delay adjustment (4)

fdel<0>

vreg<1>

00: 1.8V

10: 2.7V

01: 2.0V

11: 3.3V

External Regulated voltage (VP_

REG) setting

vreg<0>

rreg<1>

00: disabled

10: 50

01: 100

11: 25

External Regulator enable and

output resistance setting

rreg<0>

dr8

Reserved for internal use

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