AS3953B datasheet(13/65 Pages) AMSOSRAM

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Page 12

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[v1-04] 2016-Jan-07

AS3953B − Detailed Description

Power Manager

Power manager is controlling the positive supply voltage of the

PICC Logic, EEPROM and SPI Interface (VDD). Its inputs are VP_

INT (rectified and regulated supply extracted from PCD field)

and the VP_SPI (SPI power supply from external).

In standby mode, when the AS3953B is not in a PCD field

(condition is that rectified supply voltage is below HF_PON

threshold) and the SPI is not active (/SS is high) the VDD supply

is disconnected not to consume on VP_SPI. The only

consumption on VP_SPI is leakage of level shifters and SPI pins.

When the AS3953B is placed in a PCD field the VDD is connected

to VP_INT. This happens once the VP_INT level is above the HF_

PON threshold.

VP_SPI is connected to VDD only when the AS3953B is not in

the PCD field (rectified supply voltage is below HF_PON

threshold) and the SPI interface is activated by pulling /SS signal

low. The switch to VP_SPI is controlled by /SS signal. The

deactivation is delayed by 0.7ms min., thus the switch stays on

in case the time between successive SPI activations is short.

During EEPROM writing, which is activated over the SPI, the

switch is also active.

At activation of the switch the time between the falling edge

of /SS signal and rising edge of SCLK has to be at least 50μs to

allow charging of internal VDD buffer capacitor and expiration

of POR signal. Please note that the only SPI operations, which

are allowed in this mode, are reading and writing of the EEPROM

and registers.

Figure 12:

Power Manager Concept

DELAY

VP_INT

VP_SPI

VDD

PON

/SS

EEPROM

WRITE

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