AD4080BBCZ datasheet(65/94 Pages) AD

65 / 94 page

Data Sheet

AD4080

DIGITAL FEATURES

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Rev. A | 65 of 94

Filter Decimation Configuration

Configuration of the digital filter is done through the filter configura-

tion register (see the Filter Configuration Register section, Address

0x29). The FILTER_SEL bits select the active filtering path (that

is, what filters are active), with each path having different allowed

decimation rates (see Table 29).

Table 29. Digital Filters Decimation Options According to FILTER_SEL Bits

Value

FILTER_SEL

Bits Value

Active Filter

Allowed Decimation Rates

0b00

No filtering (default)

No decimation

0b01

SINC1 filter

2, 4, 8, 16, 32, 64, 128, 256,

512, 1024

0b10

SINC5 filter

2, 4, 8, 16, 32, 64, 128, 256

0b11

SINC5 + compensation filter

4, 8, 16, 32, 64, 128, 256, 512

The decimation factor is set via the SINC_DEC_RATE bits in the

filter configuration register (see Table 62 for the encoding).

The readiness of new filter data can be indicated to the host

controller via a GPIO pin by setting one of GPIO_x_SEL bits in

either GPIO Configuration B register (see the GPIO Configuration B

(see the GPIO Configuration C Register section, Address 0x1B) to

0011 (filter result ready (active low)). Until new data is available

to the interface, the data from the previous result remains in the

output shift register. The user must ensure that the same LVDS

clock rate is maintained, and the user can either reread or disregard

the repeated result data, which is shown in Figure 96, where a

decimate by 4 example is used.

Figure 96. Digital Filter Decimate by 4 Frame Overview

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