AD4080BBCZ datasheet(89/94 Pages) AD

89 / 94 page

Data Sheet

AD4080

CONFIGURATION REGISTERS

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Rev. A | 89 of 94

General Configuration Register

Address: 0x1C, Reset: 0x00, Name: GENERAL_CONFIG

Figure 132. General Configuration Register

Table 55. Bit Descriptions for GENERAL_CONFIG

Bits

Bit Name

Description

Reset

Access

INT_EVENT_EN

Internal Event Detection Enable. ADC result or filtered data is only used for internal event detection after

this bit is set to 1.

0x0

R/W

0: Internal event detection is disabled.

1: Internal event detection is enabled.

HI_ROUTE

High Detection Route. Allows high detection status to be used for FIFO event detection, status register,

and alert function (via the GPIO).

0x0

R/W

0: Mask High Detection.

1: Route High Detection to Alert Pin, Status Register, and FIFO.

LO_ROUTE

Low Detection Route. Allows low detection status to be used for FIFO event detection, status register,

and alert function (via the GPIO).

0x0

R/W

0: Mask Low Detection.

1: Route Low Detection to Alert Pin, Status Register, and FIFO.

ADC_CNV_ERR_ROUTE

ADC Conversion Error Route. Allows ADC conversion error status to be routed to the status register and

alert function (via the GPIO).

0x0

R/W

0: Mask ADC Conversion Error.

1: Route ADC Conversion Error to Alert Pin and Status Register.

[3:2]

RESERVED

Reserved. Write 0b0 to these bits.

0x0

[1:0]

FIFO_MODE

Conversion Data FIFO Mode.

0x0

R/W

00: FIFO Disabled.

01: Immediate Trigger Mode.

10: Event Trigger Capture, Read Latest WATERMARK.

11: Event Trigger Capture Mode, Read All FIFO.

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