FN8976 Rev.6.03

Page 4

Mar 28, 2024

ISL70024SEH, ISL73024SEH Datasheet

2.

Pin Information

2.1

Pin Assignments

2.2

Pin Descriptions

4 Ld SMD

Pin Number

Pin

Name

Description

1

S

Source connection for the GaN FET.

2SUB

Substrate connection for the GaN FET which is internally shorted in to source. Tie this pin to source

on the PCB.

3

D

Drain connection for the GaN FET.

4G

Gate connection for the GaN FET. Minimize trace inductance from driver to reduce over-stressing the

gate.

NA

Lid

Internally tied to the source pin.

Note: The ESD triangular mark indicates Pin #1. It is a part of the device

marking and is placed on the lid in the quadrant where Pin #1 is located.

Bottom View

(1) S

(4)

(2)

(3) D

Top View

Pin #1 Index Area

(4) G

(2) SUB

(1) S

(3) D

G

SUB