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VLSI
Solution
y
VS1103b
VS1103B
5. SPI BUSES
5.7 SPI Examples with SM SDINEW and SM SDISHARED set
5.7.1 Two SCI Writes
0
1
2
3
30
31
1
0
1
0
0
0
0
0
0
0
X
X
XCS
SCK
SI
2
32
33
61
62
63
SCI Write 1
SCI Write 2
DREQ
DREQ up before finishing next SCI write
Figure 9: Two SCI Operations.
Figure 9 shows two consecutive SCI operations. Note that xCS must be raised to inactive state between
the writes. Also DREQ must be respected as shown in the figure.
5.7.2 Two SDI Bytes
1
2
3
XCS
SCK
SI
7
6
5
4
3
1
0
7
6
5
2
1
0
X
SDI Byte 1
SDI Byte 2
0
6
7
8
9
13
14
15
DREQ
Figure 10: Two SDI Bytes.
SDI data is synchronized with a raising edge of xCS as shown in Figure 10. However, every byte doesn’t
need separate synchronization.
Version 1.01, 2007-09-03
21
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