ADC14DC080 datasheet(3/26 Pages) TI2

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DRGND

VDR

DRGND

AGND

ADC14DC080

www.ti.com

SNAS463B – SEPTEMBER 2008 – REVISED APRIL 2013

Pin Descriptions and Equivalent Circuits (continued)

Pin No.

Symbol

Equivalent Circuit

Description

Reference Voltage. This device provides an internally developed

1.2V reference. When using the internal reference, VREF should be

decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series

VREF

inductance (ESL) capacitor.

This pin may be driven with an external 1.2V reference voltage.

This pin should not be used to source or sink current when the

internal reference is used.

DIGITAL I/O

This is a four-state pin controlling the input clock mode and output

data format.

OF/DCS = VA, output data format is 2's complement without duty

cycle stabilization applied to the input clock.

OF/DCS = AGND, output data format is offset binary, without duty

OF/DCS

cycle stabilization applied to the input clock.

OF/DCS = (2/3)*VA, output data is 2's complement with duty cycle

stabilization applied to the input clock.

OF/DCS = (1/3)*VA, output data is offset binary with duty cycle

stabilization applied to the input clock.

The clock input pin.

CLK

The analog inputs are sampled on the rising edge of the clock input.

This is a two-state input controlling Power Down.

PD_A

PD = VA, Power Down is enabled and power dissipation is reduced.

PD_B

PD = AGND, Normal operation.

Digital data output pins that make up the 14-bit conversion result for

40-49,

DA0-DA9,

Channel A. DA0 (pin 40) is the LSB, while DA13 (pin 55) is the MSB

52-55

DA10-DA13

of the output word. Output levels are CMOS compatible.

Digital data output pins that make up the 14-bit conversion result for

21-24,

DB0-DB3,

Channel B. DB0 (pin 21) is the LSB, while DB13 (pin 36) is the MSB

27-36

DB4-DB13

of the output word. Output levels are CMOS compatible.

Data Ready Strobe. The data output transition is synchronized with

DRDY

the falling edge of this signal. This signal switches at the same

frequency as the CLK input.

ANALOG POWER

Positive analog supply pins. These pins should be connected to a

8, 16, 17, 58,

quiet source and be bypassed to AGND with 0.1 µF capacitors

located close to the power pins.

The ground return for the analog supply.

1, 4, 12, 15,

AGND

The exposed pad on back of package must be soldered to ground

Exposed Pad

plane to ensure rated performance.

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