FS310 datasheet(15/40 Pages) TTELEC

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General Note

TT Electronics reserves the right to make changes in product specification without

notice or liability. All information is subject to TT Electronics’ own data and is

considered accurate at time of going to print.

TT Electronics | OPTEK Technology

2900 E. Plano Parkway, St 200, Plano, TX 75074, USA | Ph: +1 972 323 2200

www.ttelectronics.com | sensors@ttelectronics.com

Rev C, 4/27/2023

Page 15

FlexSense® I-Series Programmable

Incremental Encoder

FS210/FS310 Datasheet

Details of quadrature-track output-pin operation are controlled by the QCFG register as shown below:

Quad-Track Configuration Register (QCFG: [0x0884]):

Table 10. QCFG register definition.

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

LSB

SE_DZ

NBWL

D_AZ

INTP

Table 11. QCFG field description.

Bits

Definition

INTP

Digital interpolation or divide-down factor:

0000: No Interpolation

0001: 2x multiply

0010: 4x multiply

0011: 8x multiply

0100: Reserved

0101: x2 divide

0110: x4 divide

0111: x8 divide

1000: x16 divide

1001: x32 divide

1010: x64 divide

1011: x128 divide

1100: x256 divide

1101: x512 divide

1110: x1,024 divide

1111: x2,048 divide

D_AZ

Analog/digital control for quadrature-track outputs

Analog outputs

Digital outputs

NBWL

Reserved: Do not change from power-up default (00)

SE_DZ

Single-ended / differential digital output control. (no effect if D_AZ bit is 0)

Differential (AOUT_P_DIG, BOUT_P_DIG, AOUT_N_DIG, BOUT_N_DIG all driven when D_AZ = 1)

Single-ended (AOUT_P_DIG and BOUT_P_DIG driven; AOUT_N_DIG and BOUT_N_DIG not driven

when D_AZ = 1)

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