FS310 datasheet(31/40 Pages) TTELEC

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General Note

TT Electronics reserves the right to make changes in product specification without

notice or liability. All information is subject to TT Electronics’ own data and is

considered accurate at time of going to print.

TT Electronics | OPTEK Technology

2900 E. Plano Parkway, St 200, Plano, TX 75074, USA | Ph: +1 972 323 2200

www.ttelectronics.com | sensors@ttelectronics.com

Rev C, 4/27/2023

Page 31

FlexSense® I-Series Programmable

Incremental Encoder

FS210/FS310 Datasheet

Comparator/Buffer Enable Register (CBFEZ: [0x088B])

Table 34. CBFEZ register definition.

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

LSB

RSVD

ZCEZ

QICEZ

RSVD

Table 35. CBFEZ field description.

Bits

Description

QICEZ

Quad-track interpolated comparator enable bit:

Enable quad-track comparators required to produce interpolated outputs (power-on default)

Disable quad-track comparators required to produce interpolated outputs

ZCEZ

Index-track comparator enable bit:

Enable index-track comparator (power-on default)

Disable index-track comparator

RSVD

Reserved; do not modify from power-on default value (0)

Miscellaneous Control Register (MISC: [0x088D])

Table 36. MISC register definition.

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

LSB

RSVD

PMOUT

RSVD

Table 37. MISC field description.

Bits

Description

PMOUT

Preventive-maintenance output control bits:

00:

Disable preventive-maintenance outputs (power-on default)

11:

Enable preventive-maintenance outputs

01, 10:

Prohibited

RSVD

Reserved; do not modify from power-on default value (<7:6> = 00; <3:0> = 0001)

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