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F0448 데이터시트(PDF) 1 Page - Renesas Technology Corp |
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F0448 데이터시트(HTML) 1 Page - Renesas Technology Corp |
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1 / 43 page ![]() Datasheet F0448 Dual Matched Broadband RF DVGA 3.3GHz to 4.2GHz X0008129 Rev.1.4 Feb 17, 2021 Page 1 © 2018 Renesas Electronics The F0448 is a 3.3GHz to 4.2GHz dual RF digital variable gain amplifier (DVGA) designed for use in receivers. This dual RF DVGA provides two independent receiver channels each with 13dB typical maximum gain and 6dB noise figure designed to operate with a single +5V supply. For each channel, gain control is split into three separate attenuators: DSA0, a single 6dB step using a single control pin; DSA1, a 23dB SPI-controlled gain adjustment in 1dB steps; and DSA2, includes 18dB attenuation in 6dB steps controlled using two control pins. The F0448 offers +37dBm nominal output IP3 using 220mA total ICC. This device is packaged in a 6 × 6 mm, 36-QFN with 50Ω single-ended RF input and RF output impedances for ease of integration into the signal- channel lineup for each of the two channels. Figure 1. Block Diagram Features ■ RF Frequency Range: 3.3GHz to 4.2GHz ■ Dual Channel RF amp and DSAs for Diversity / MIMO Receivers ■ < 2dB overshoot between DSA transitions ■ 13dB typical maximum gain at 3.6GHz ■ DSA0: Single 6dB coarse step ■ DSA1: 23dB total gain range in 1dB steps ■ DSA2: 18dB gain range in 6dB steps ■ +37dBm OIP3 at 3.6GHz ■ 6dB Noise figure at 3.6GHz ■ +5V Supply voltage ■ ICC = 220mA ■ Independent standby: 7mA standby current ■ SPI interface for DSA1 ■ 1-bit control for DSA0 ■ 2-bit control for DSA2 ■ 50Ω input and output impedance ■ Internally matched ■ Temperature range: -40°C to +105°C ■ 6 × 6 × 0.75 mm, 36-QFN package Applications ■ Multi-mode, Multi-carrier Receivers ■ PHS/PAS Base Stations ■ Distributed Antenna Systems ■ Digital Radio DATA CLK CSb RFIN_A RFIN_B RFOUT_A RFOUT_B DSA0A DSA2A F0448 STBY RF AMP A Glitch - Free TM Glitch - Free TM Zero - Distortion TM Zero - Distortion TM VCTRL0 DSA1A 6dB 23dB 18dB VCTRL1 VCTRL2 RF AMP B 6dB 23dB 18dB DSA0B DSA2B DSA1B Decode Logic / Bias 2 2 2 2 2 |
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