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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CC1050-RTR1 데이터시트(PDF) 7 Page - Texas Instruments |
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CC1050-RTR1 데이터시트(HTML) 7 Page - Texas Instruments |
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7 / 43 page  CC1050 SWRS044 Page 7 of 40 Pin Assignment Pin no. Pin name Pin type Description 1 AVDD Power (A) Power supply (3 V) for analog modules (PA) 2 AGND Ground (A) Ground connection (0 V) for analog modules (PA) 3 AGND Ground (A) Ground connection (0 V) for analog modules (PA) 4 AGND Ground (A) Ground connection (0 V) for analog modules (VCO and prescaler) 5 L1 Analog input Connection no 1 for external VCO tank inductor 6 L2 Analog input Connection no 2 for external VCO tank inductor 7 AVDD Power (A) Power supply (3 V) for analog modules (VCO and prescaler) 8 CHP_OUT Analog output Charge pump current output when external loop filter is used The pin can also be used as PLL Lock indicator. Output is high when PLL is in lock. 9 R_BIAS Analog output Connection for external precision bias resistor (82 k Ω, ± 1%) 10 AGND Ground (A) Ground connection (0 V) for analog modules (backplane) 11 AVDD Power (A) Power supply (3 V) for analog modules (general) 12 AGND Ground (A) Ground connection (0 V) for analog modules (general) 13 XOSC_Q2 Analog output Crystal, pin 2 14 XOSC_Q1 Analog input Crystal, pin 1, or external clock input 15 AGND Ground (A) Ground connection (0 V) for analog modules (guard) 16 DGND Ground (D) Ground connection (0 V) for digital modules (substrate) 17 DVDD Power (D) Power supply (3 V) for digital modules 18 DGND Ground (D) Ground connection (0 V) for digital modules 19 DI Digital input Data input in transmit mode 20 DCLK Digital output Clock for data in transmit mode 21 PCLK Digital input Programming clock for 3-wire bus 22 PDATA Digital input/output Programming data for 3-wire bus. Programming data input for write operation, programming data output for read operation 23 PALE Digital input Programming address latch enable for 3-wire bus 24 RF_OUT RF output RF signal output to antenna A=Analog, D=Digital (Top View) AGND AGND AGND L1 L2 AVDD AGND 1 2 3 5 4 6 7 8 10 11 12 9 PALE PDATA PCLK DCLK DI DGND DVDD DGND AGND XOSC_Q1 AGND XOSC_Q2 24 23 22 20 21 19 18 17 15 14 13 16 RF_OUT AVDD CHP_OUT R_BIAS AVDD AGND AGND AGND L1 L2 AVDD AGND 1 2 3 5 4 6 7 8 10 11 12 9 PALE PDATA PCLK DCLK DI DGND DVDD DGND AGND XOSC_Q1 AGND XOSC_Q2 24 23 22 20 21 19 18 17 15 14 13 16 RF_OUT AVDD CHP_OUT R_BIAS AVDD Not Recommended for New Designs |
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