SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

LP3958

SNVS423C – JANUARY 2006 – REVISED MARCH 2013

www.ti.com

GPIO DATA (07H)

Name

Bit

Description

DATA[2:0]

2:0

Data bits

GPIO control register is used to set the direction of each GPIO pin. For example, by setting OEN0 bit high the

GPIO[0]/PWM pin acts as a logic output pin with data defined DATA0 in GPIO data register. Note, that the

EN_PWM_PIN bit overrides OEN0 state by forcing GPIO[0]/PWM to act as PWM input. GPIO[1] and GPIO[2]

pins can be selected to be inputs or outputs, defined by OEN1 and OEN2 bit status. PWM functionality is valid

only for GPIO[0]/PWM pin. GPIO data register contains the data of GPIO pins. When output direction is selected

to GPIO pin, then GPIO data register defines the output pin state. When GPIO data register is read, it contains

the state of the pin despite of the pin direction.

Table 4. Logic Interface Characteristics(VDDIO = 1.65V...VDD1,2 unless otherwise noted)

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

LOGIC INPUT SCL, SDA, GPIO[0:2]

VIL

Input Low Level

0.2×VDDIO

V

VIH

Input High Level

0.8×VDDIO

V

II

Logic Input Current

−1.0

1.0

µA

fSCL

Clock Frequency

400

kHz

LOGIC INPUT NRST

VIL

Input Low Level

0.5

V

VIH

Input High Level

1.2

V

II

Input Current

-1.0

1.0

µA

tNRST

Reset Pulse Width

10

µs

LOGIC OUTPUT SDA

VOL

Output Low Level

ISDA = 3mA

0.3

0.5

V

VOH

Output High Level

ISDA = -3mA

VDDIO − 0.5

VDDIO − 0.3

IL

Output Leakage Current

VSDA = 2.8V

1.0

µA

LOGIC OUTPUT GPIO[0:2]

VOL

Output Low Level

IGPIO = 3 mA

0.3

0.5

V

VOH

Output High Level

IGPIO = −3 mA

VDDIO − 0.5

VDDIO − 0.3

V

IL

Output Leakage Current

VGPIO = 2.8V

1.0

µA

I

2C Compatible Interface

I2C SIGNALS

The SCL pin is used for the I2C clock and the SDA pin is used for bidirectional data transfer. Both these signals

need a pull-up resistor according to I2C specification.

I2C DATA VALIDITY

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when CLK is LOW.

Figure 22. I2C Signals: Data Validity

20

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