PUSB3FR6

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2015. All rights reserved.

Product data sheet

Rev. 1 — 25 February 2015

6 of 12

NXP Semiconductors

PUSB3FR6

ESD protection for ultra high-speed interfaces

The device uses an advanced clamping structure showing a negative dynamic resistance.

This snapback behavior strongly reduces the clamping voltage to the system behind the

ESD protection during an ESD event. Do not connect unlimited DC current sources to the

data lines to avoid keeping the ESD protection device in snap-back state after exceeding

breakdown voltage (due to an ESD pulse for instance).

tp = 100 ns; Transmission Line Pulse (TLP)

tp = 100 ns; Transmission Line Pulse (TLP)

Fig 6.

Dynamic resistance with positive clamping;

typical values

Fig 7.

Dynamic resistance with negative clamping;

typical values

tp = 5 ns; Very-Fast TLP (VF-TLP)

tp = 5 ns; Very-Fast TLP (VF-TLP)

Fig 8.

Dynamic resistance with positive clamping;

typical values

Fig 9.

Dynamic resistance with negative clamping;

typical values

VCL (V)

025

20

10

15

5

aaa-016884

10

15

5

20

25

IPP

(A)

0

VCL (V)

-25

0

-5

-15

-10

-20

aaa-016885

-15

-10

-20

-5

0

IPP

(A)

-25

VCL (V)

025

20

10

15

5

aaa-016886

10

15

5

20

25

IPP

(A)

0

VCL (V)

-25

0

-5

-15

-10

-20

aaa-016887

-15

-10

-20

-5

0

IPP

(A)

-25