PCM1741ESLASH2K datasheet(8/24 Pages) TI2

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PCM1741

SBAS175

SYSTEM CLOCK AND RESET

FUNCTIONS

SYSTEM CLOCK INPUT

The PCM1741 requires a system clock for operating the

digital interpolation filters and multilevel delta-sigma modu-

lators. The system clock is applied at the SCK input (pin 16).

Table I shows examples of system clock frequencies for

common audio sampling rates.

Figure 1 shows the timing requirements for the system clock

input. For optimal performance, it is important to use a clock

source with low phase jitter and noise. The PLL1700 multi-

clock generator from Texas Instruments is an excellent choice

for providing the PCM1741 system clock.

POWER-ON RESET FUNCTIONS

The PCM1741 includes a power-on reset function, as shown in

Figure 2. With the system clock active, and VDD > 2.0V (typical

1.6V to 2.4V), the power-on reset function will be enabled. The

initialization sequence requires 1024 system clocks from the

time VDD > 2.0V. After the initialization period, the PCM1741

will be set to its reset default state, as described in the Mode

Control Register section of this data sheet.

During the reset period (1024 system clocks), the analog

outputs are forced to the bipolar zero level, or VCC/2. After

the reset period, the internal register is initialized in the next

1/fS period and, if SCK, BCK, and LRCK are provided

continuously, the PCM1741 provides proper analog output

with unit group delay against the input data.

FIGURE 1. System Clock Input Timing.

SAMPLING

FREQUENCY

256fS

384fS

512fS

768fS

8kHz

2.0480

3.0720

4.0960

6.1440

16kHz

4.0960

6.1440

8.1920

12.2880

32kHz

8.1920

12.2880

16.3840

24.5760

44.1kHz

11.2896

16.9344

22.5792

33.8688

48kHz

12.2880

18.4320

24.5760

36.8640

88.2kHz

22.5792

33.8688

45.1584

See Note (1)

96kHz

24.5760

36.8640

49.1520

See Note (1)

NOTE: (1) The 768fS system clock rate is not supported for fS > 64kHz.

TABLE I. System Clock Rates for Common Audio Sampling Frequencies.

SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)

FIGURE 2. Power-On Reset Timing.

1024 System Clocks

Reset

Reset Removal

Internal Reset

2.4V

2.0V

1.6V

System Clock

Don't Care

SCKH

SCKL

2.0V

0.8V

System Clock

System clock pulse

cycle time(1)

“H”

“L”

System Clock Pulse Width HIGH t

SCKH: 7ns (min)

System Clock Pulse Width LOW t

SCKL: 7ns (min)

NOTE: (1) 1/256f

S, 1/384fS, 1/512fS, and 1/768fS.

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