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ZERO FLAGS

Zero-Detect Condition

Zero Output Flags

PCM1742

SBAS176A – DECEMBER 2000 – REVISED APRIL 2005

Zero detection for each output channel is independent from the other. If the data for a given channel remains at a

0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that channel.

Given that a zero-detect condition exists for one or more channels, the zero-flag pins for those channels are set

to a logic-1 state. The zero-flag pins for each channel are ZEROL (pin 12) and ZEROR (pin 11). These pins can

be used to operate external mute circuits, or used as status indicators for a microcontroller, audio signal

processor, or other digitally controlled function.

The active polarity of the zero-flag output can be inverted by setting the ZREV bit of control register 22 to 1. The

reset default is active-high output, or ZREV = 0.

The L-channel and R-channel common zero flag can be selected by setting the AZRO bit of control register 22

to 1. The reset default is L-channel and R-channel independent zero flag, or AZRO = 0.

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