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PCM1742

V

CC

V

DD

DGND

Output

Circuits

RF Choke or Ferrite Bead

Common

Ground

AGND

DIGITAL SECTION

ANALOG SECTION

V

DD

Power Supplies

+5V

+V

S

AGND

REG

−V

S

Digital Logic

and

Audio

Processor

THEORY OF OPERATION

+

Z−1

8−Level Quantizer

+

Z−1

+

Z−1

−

+

Z−1

+

+

8f

S

64f

S

PCM1742

SBAS176A – DECEMBER 2000 – REVISED APRIL 2005

APPLICATION INFORMATION (continued)

Figure 31. Single-Supply PCB Layout

The delta-sigma section of the PCM1742 is based on an 8-level amplitude quantizer and a fourth-order noise

shaper. This section converts the oversampled input data to 8-level delta-sigma format. A block diagram of the

8-level delta-sigma modulator is shown in Figure 32. This 8-level delta-sigma modulator has the advantage of

stability and clock jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator. The combined

oversampling rate of the delta-sigma modulator and the interpolation filter is 64 fS.

The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown in Figure 33. The

enhanced multilevel delta-sigma architecture also has advantages for input clock-jitter sensitivity due to the

multilevel quantizer, with the simulated jitter sensitivity, as shown in Figure 34.

Figure 32. 8-Level Delta-Sigma Modulator

27